Specification

10 x 19-bit SDLC/HDLC frame status FIFO array
a 14-bit SDLC/HDLC frame byte counter
automatic SDLC/HDLC opening flag transmission
automatic SDLC/HDLC Tx Underrun/EOM flag resetting
automatic SDLC/HDLC Tx CRC generator presetting
RTS pin synchronization to closing SDLC/HDLC flag
DTR/REQ deactivation delay significantly reduced
external PCLK to RxC or TxC synchronization requirement eliminated for PCLK divide by- four operation
complete SDLC/HDLC CRC character reception
reduced INT response time
Write data setup time to rise edge of WR requirement eliminated
Write Registers WR3, WR4, WR5, and WR10 made readable